Electrical Engineering UPSC PYQ 2025

Answer all parts: <!--qid:MAINS_2025_Electrical_Engineering-I_Q5-->

Answer the following sub-parts: Sketch the approximate root-locus plot for a time-delay system approximated by the transfer function G(s) = K(1 – s/2) / [s(s + 1)(1 + s/2)]. Also compute the largest value of K for which the system is stable under unity feedback and verify this value from the root-locus plot. [10M] The signal-flow graph of a system is as shown below. Determine the overall transmission R(s)/Y(s) and evaluate the sensitivity of the output to variations in K1 at s = 10. What would be the value of sensitivity obtained under DC condition, i.e. s = 0? [10M] <!--qid:MAINS_2025_Electrical_Engineering-II_Q3-->

Answer the following sub-parts (a) to (c): <!--qid:MAINS_2025_Electrical_Engineering-II_Q2-->

Answer the following sub-parts (a) to (e): <!--qid:MAINS_2025_Electrical_Engineering-II_Q1-->

Consider the circuit of an operational amplifier given here in which Zener diodes Z1 and Z2 are having reverse breakdown voltage = 7.4 V and forward voltage drop = 0.6 V. (i) Draw the output voltage waveform showing voltage value with time and calculate frequency of output waveform. (ii) Modify the circuit for duty cycle factor D = 0.25 by replacing R1 from combination of suitable resistances and diodes, so that output frequency is not changed. Draw the output voltage waveform showing voltage value with time and calculate frequency of output waveform. Modify the circuit for duty cycle factor D = 0.25 by replacing R1 from combination of suitable resistances and diodes, so that output frequency is not changed. <!--qid:MAINS_2025_Electrical_Engineering-I_Q2-->

Consider the Boolean function : F(A, B, C, D) = Σ m (1, 3, 4, 11, 12, 13, 14, 15) Implement it with a 4-to-1 multiplexer and external gates. Connect inputs A and B to the selection lines. Input to the four data lines is a function of the variables C and D which are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01, 10 and 11. Functions are to be implemented with external gates. <!--qid:MAINS_2025_Electrical_Engineering-I_Q3-->

Answer the following: <!--qid:MAINS_2025_Electrical_Engineering-I_Q6-->

Answer the following sub-parts: <!--qid:MAINS_2025_Electrical_Engineering-I_Q4-->